We deliver the possibilities of data. YOU define what’s possible.
The Memory Technology Group is at the core of the Legacy SanDisk Engineering Organization which Western Digital owns. We are building a cutting edge 3D memory in our multiple billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost but on quality. The Memory Technology organization is a strategic entity for the company, and we are growing. Our group functions as a start-up within WDC, and offers a creative, fast paced, entrepreneurial work environment where you’ll be at the center of WDC innovation.
We are looking for an experienced Designers to lead and deliver projects for our Memory Design team as well as talented and highly motivation junior engineers. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and who has a great track record for delivering innovative results.
You will need to think creatively about the memory as we do take pride in our craftsmanship. We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.
Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative and focused team!
ESSENTIAL DUTIES AND RESPONSIBILITIES:
In this position, the individual will be responsible for performing place and route at block and full chip level, will work on next generation 3D flash memory chip design, and contribute from RTL to GDS on block level designs.
Specific tasks will include but not limiting the following:
- design floor planning, place and route.
- CTS (Clock Tree Synthesis) and timing analysis.
- physical design verification and debug.
- ECO (Engineering Change Order) on existing database.
- Perform physical implementation steps which include floor planning, place and route, power grid planning, clock tree design, timing closure, ECO, LVS/DRC.
- Work with design and synthesis team to achieve area, timing and power targets.
- Develop physical design methodologies and automation scripts for various implementation steps.
- MSEE or MSCS with 5+ year experience of digital physical design.
- Experience with RTL 2 GDSII concepts and flows.
- Requires good programming/scripting skills in SKILL, TCL, perl or Python.
- STA (Static Timing Analysis) experience.
- Experience with industry standard toolsets from Cadence (SOC) or Synopsys (ICC).
- Experience of physical verification such as DRC, LVS and XOR.
- Excellent communication skills, both written and verbal.
- Ability to work in a team environment.
ABOUT WESTERN DIGITAL
Western Digital Corporation is the world’s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions. Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess.
Western Digital is an equal opportunity employer. We are committed to providing equal employment opportunity for all applicants and employees. Western Digital does not unlawfully discriminate and complies with the laws and regulations set forth in the following EEO Is The Law poster: Equal Employment Opportunity Is The Law
Western Digital participates in the E-Verify program in the US. For more information click here. Este empleador participa in E-Verify.