ASIC Design Engineer
Req ID: JR-0000040850
We deliver the possibilities of data. YOU define what’s possible.
Responsibilities will include complete ownership of sub chip PnR environment, clock tree design and driving Place-And-Route flow for full chip convergence and timing closer.
The individual must have a strong desire to learn and must be a go getter.
Having exposure to Physical Verification flow for DRC and LVS closure for blocks is preferred.
Ability to work with minimal supervision and drive to exceed expectations is a must.
Good verbal and written communication skills are required.
This position requires a Master’s Degree in Electrical Engineering or Computer Science with a minimum of 8 to 12 years of hands on experience in sub chip / full chip Place-And-Route flow with emphasis on 16 nm and 7nm designs.
Proficiency in ICC / ICC II and experience in PERL/TCL/Shell scripting is a must.
ABOUT WESTERN DIGITAL
Western Digital Corporation is the world’s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions. Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess.