We deliver the possibilities of data. YOU define what’s possible.
The Memory Technology Group is at the core of the Legacy SanDisk Engineering Organization which Western Digital owns. We are building a cutting edge 3D memory in our multiple billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost but on quality. The Memory Technology organization is a strategic entity for the company, and we are growing. Our group functions as a start-up within WDC, and offers a creative, fast paced, entrepreneurial work environment where you’ll be at the center of WDC innovation.
We are looking for an experienced Designers to lead and deliver projects for our Memory Design team as well as talented and highly motivation junior engineers. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and who has a great track record for delivering innovative results.
You will need to think creatively about the memory as we do take pride in our craftsmanship. We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.
Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative and focused team!
ESSENTIAL DUTIES AND RESPONSIBILITIES:
· Perform design flow from Netlist to GDS, Floor Plan, RTL to gate level synthesis, LEC, Constraint file generation, Place and Route including auto/custom-placement & routing, Clock Tree Synthesis, Static Timing Analysis on post route gate level designs
· Perform physical verification and clean LVS / DRC / ANTENNA
· Able to analyze complex multi-cycle timing constraints for both setup and hold timing requirements
· Must understand Multi-corner Multimode methodology for synthesis and STA flow
· Develop logic synthesis scripts, static timing scripts, timing eco scripts, physical design methodologies and automation scripts for various implementation steps
· Experience to work with logic designer to understand timing requirements
· Work with design, layout team to achieve area, timing and power targets
· Excellent debugging skills, particular in synthesis and timing analysis
· Maintain accurate and thorough documentation of work, design flows and reports
Complete ownership of entire synthesis and physical development process
· An individual must have proven ability to achieve results in a fast moving, dynamic environment
· Excellent communication skills, both written and verbal.
· Self-motivated and ability to work in a team environment both on the same team and outside of the team
· Experience with standard toolsets Synopsys (Design Compiler/Prime Time/ICC/ICC2) or Cadence
· Experience of physical verification tools Synopsys or Cadence such as DRC, LVS, Antenna fixes and XOR
· Excellent skills in programming and scripting languages like Shell, Python, Perl or TCL
· Knowledge of EDA tools RC-Extraction, SPICE simulators, Cadence Virtuoso schematic/layout editors
· Master's degree in Electrical Engineering and/or Computer Engineering with 12+ years of experience OR Bachelor's degree in Electrical Engineering and/or Computer Engineering with 15+ years of experience
ABOUT WESTERN DIGITAL
Western Digital Corporation is the world’s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions. Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess.
Western Digital is an equal opportunity employer. We are committed to providing equal employment opportunity for all applicants and employees. Western Digital does not unlawfully discriminate and complies with the laws and regulations set forth in the following EEO Is The Law poster: Equal Employment Opportunity Is The Law.
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