The Tools team is developing a wide range of FPGA solution for post silicon validation
for memory devices across Western Digital.
team is looking for a talented, energetic Verification team leader with communication
capabilities and proven ability to lead a small group of engineers (10) in a
multi-disciplinary environment with a variety of interfaces. We are looking for
a talented with high intercommunication skills and motivation to own the
verification environment infrastructure .
At least 7 years of experience in Asic or FPGA
Proven experience in leading a small group of ~10 engineers
Knowledge in System Verilog.
Ability to plan and write verification components
Knowledge in advanced verification infrastructures such as
UVM, VMM, etc. – a must!!
Excellent knowledge of one or more scripting languages
(TCL, Perl, Python)
Experience as RTL Designer – an advantage
Deep knowledge of the following tools:
ü NCSim – advantage