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Senior Manager ASIC Design Engineering

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Location: Bangalore, KA, India 
Req ID: JR-0000038385


  • Education requirements/Preference: Bachelor or Master Degree in Electrical/Electronics Engineering

    The Ideal Individual must have:

    • Proven ability to lead SoC Design team and achieve results in a fast moving, dynamic environment.
    • Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
    • A proven desire to work as a team member, both on the same team and outside of the team.
    • The ability to troubleshoot and analyze complex problems.
    • Ability to multi-task and meet deadlines.

    Required Experience:

    • 12-20 years’ experience in Frontend ASIC design flow.
    • Should have 3-6 Years of Experience in Managing Design/Verification team
    • Should have 3-6 years’ experience as a SoC Design team leader in leading designs from specification through Silicon debug/characterization.
    • Should be conversant with ARM/ARC based SoC Architecture
    • Should have taped out atleast 2 complete SoC at 40/28/16nm nodes
    • Should have understanding of challenges of FPGA emulation of design.
    • Should have expertise in Verilog and/or VHDL
    • Should have good insight Backend flow.
    • Should have experience in a multi-site environment, interacting with teams in other sites.
    • Should possess proven managerial skills and communication skills
    • Good to have knowledge of USB/SD/SATA/PCIe Protocols

    Tasks to be performed & areas of responsibility

    • Will be responsible for Leading SoC from Specification to final Product.
    • Will be responsible for overall interface management of Design IPs, Analog IPs, Verification IPs, FPGA Validation Platform Selection
    • Will be responsible for team formation with inputs from Design and Verification Leads
    • Will be to provide leadership in terms of end-to-end technical management
    • Will be responsible for building team and developing processes
    • Will be responsible of IP Vendor Co-ordination in collaboration with IP Team
    • Will be responsible for IP selection and IP reviews with internal and external vendors
    • Will be responsible for project status communication with higher management
    • Will be responsible of maintaining system level view of SoC and its external interfaces