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Staff Engineer, ASIC Development Engineering

Location: Bangalore, KA, India 
Req ID: JR-0000038106


  • Education Requirements/Preference: Bachelor or Master Degree in Electrical/Electronics Engineering

    Required Experience:
    • 5+ years of experience in full custom layout for Analog and mixed signal circuits
    • Should have hands-on experience in custom layout for multi-Gb/s SERDES sub-circuits (i.e. high speed Rx/Tx, PLL, CDR, VGA, CTLE, DFE, S2P/P2S, etc.)
    • Familiarity with custom digital layout (i.e. high speed logic paths)
    • Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding)
    • Experience in layout delivery flow – different views generation like LIB, LEF, GDS, etc.
    • Strong experience in debugging DRC, ERC and LVS issues independently.
    • Aware of layout techniques to mitigate ESD, latch-up
    • Knowledge of design for reliability (i.e. EM, IR, self-heating, etc.)
    • Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 28nm, 16nm and smaller.
    • Also should have sound understanding of IC fabrication and reliability issues
    • Full familiarity with Cadence and Mentor Graphics layout tools
    • Experience in scripting in Perl and/or Skill to develop scripts for automation is an advantage
    • Should possess good documentation, communication and presentation skills
    • Experience of working in a multi-site environment