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Technologist, R&D Engineering

Location: Bangalore, KA, India 
Req ID: JR-0000037784

Description


Experience:

               3-6 years Years of experience in the following areas:

- Functional Verification:

•Assertion Based Verification (ABV) setup
•System Verilog Assertion Hands-on (a must)
•SVA based Verification plan development
•Exposure in Verilog/System Verilog/UVM Test bench application
•Exposure in Formal based Verification
•Verification closure using coverage metrics
•RTL & Gate Level Simulations
•Proficiency in Verilog, System Verilog & Assertions
•Verification Automation using scripts  like Perl,shell,tcl/tk 
•Exposure to Analog verification will additional plus point


-Digital design Concepts
-  CMOS VLSI, Digital Circuits
-  Knowledge on Memory (preferred)
(SRAM/DRAM/ROM/Flash) Circuits/Logic
- Expertise in following CAD Tools
- NCSIM, IMC, IEV, Verdi, Jasper, VS Formal
- Cadence Schematic and layout environment

Education & Soft skills:

•Masters from a reputed School
•Strong Problem Solving
•Efficient Communication
•Team Leading & Mentoring

Job responsibilities: 

•Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
•Test Plan development for verification closure using SVA
•Testing various features at full-chip as well as module-level using targetted/random/corner-case/coverage tests,
•Run regressions and extract Code/Functional Coverage,
Debug failures and root-cause it by interacting with other teams/groups Etc