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Principal Engineer, Systems Design Engineering

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Location: Tefen, IL, Israel 
Req ID: JR-0000036758


 Define system architecture that contains FW-SW/HW/FPGA(digital) items.
 Define digital architecture (FPGA) with busses and IP block behave. 
 Define Digital blocks IP SPECs, include HL architecture of the block.
 System performance analysis.
 Ramp up evaluation platforms for system analysis. 
 Hands on FPGA for complicated blocks
> 6 years engineering experience
> 6 years in Digital design (FPGA or ASIC) on high speed.
       FPGA experience (design and implementation from RTL to P&R) - added 
       HW experience – added value

 System view and well understanding system on chip work.
 Simulation and analysis skills, modeling systems for performance analysis.
 High interpersonal skill to connect and guide engineers from different teams.
 Knowledge with popular busses and standards – PCIe, AXI4 (AMBA), DDR3/4,   TCPIP, Interconnects
 Knowledge with SW/FW architectures. 
 High capability of self-learning.
 Ability to dive into RTL code or behave to discover performance hiccups -   added value.
 SW/FW C code review - added value.

BSc/B.Tech from known university 
Master degree – added value