WDC San Jose Research Center is a premier research center with more than 120 researchers working across many technical fields including storage and systems architecture, operating systems, CPU technologies, machine learning and emerging non-volatile memories.
The job opening is for Fellow level position in the CPU project group. The main research theme of the group is microarchitecture and RTL level design of the enterprise/datacenter grade multi-core CPUs based on open instruction set architectures such as RISC-V (see riscv.org). The main emphasis of the CPU design will be enablement of novel memory centric architectures and memory interfaces, demonstrating and implementing unprecedented compute capability, memory bandwidth and scaling to 1PB scale. The team is also supporting core microarchitecture for embedded cores for SoCs and machine learning accelerators for variety of Western Digital storage and accelerator products. The CPU project team roles will include architecture, microarchitecture and RTL, design modeling, design verification, power analysis and optimization and cache coherence protocol implementation.
Ideal candidate would lead the CPU project team on conceiving, prototyping and guiding research and development of new enterprise/datecenter CPUs from architecture to RTL design, modeling and verification. The CPU team will collaborate with Western digital physical design team on physical implementation and tape-out.
Graduate level degree (MSc or PhD) in Computer science, Computer engineering, Electrical engineering or related, with a proven publication track record and implementation experience in enterprise CPU architecture and RTL design, system architecture, and operating systems.