Education Requirements/Preference: Bachelor or Master Degree in Electrical/Electronics Engineering
• 7+ years of experience in Analog and mixed signal design, should have 2-3 years of experience as a project leader
• Should have experience in leading designs from specification through Silicon debug/characterization.
• Should have hands-on experience in multi-Gbps SERDES block level designs (Rx, Tx, CDR, PLL, DLL, VGA, CTLE, DFE, voltage and current references, voltage detectors, LDOs)
• Knowledge of different CDR architectures is a plus
• Strong background in wireline communication and equalization techniques
• Sound knowledge about high-speed SERDES protocols (PCIe, SATA, USB, UFS, etc.)
• Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 28nm, 16nm and smaller.
• Should have hands-on experience in simulation of analog blocks, mixed-mode simulations, statistical simulations etc.
• Knowledge in modelling (Simulink, Matlab, VerilogA, etc.) tools will be an advantage
• Should have good insight into layouts and knowledge of ESD requirements.
• Experience in lab testing and debugging for high-speed serial links and protocol compliance is an advantage
• Should possess good documentation, communication and presentation skills
• Should have experience in a multi-site environment
Tasks to be Performed & Areas of Responsibility:
• Will be part of a team responsible for delivering next-generation PHY designs for SoCs in leading-edge CMOS process technology nodes at 28nm and beyond
• Ownership of analog and digital circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements
• Handling assigned projects independently, leading a small team of junior engineers
• Pro-actively get design issues/problems resolved
• Work closely with the layout engineers on providing requirements and guidelines