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Principal Engr, ASIC Design Verification

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Location: Chubei City, Hsinchu County, Taiwan 
Req ID: JR-0000027180


Job Description:

Job Description

Looking for ASIC Verification Engineer, responsible for.
Development of ASIC verification and Validation plans.
Development of UVM or C test cases for ASIC verification and validation to achieve comprehensive coverage.
Working with ASIC design and architecture teams to understand functionality of logic blocks of SSD controller .
Comprehending "big picture" at the ASIC architectural and system level as well as executing at the detail block level.

Education Requirements:

• Master degree in Electrical Engineering or Computer Science.

• 6+ years of applicable experience. 
• Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred. 
• Knowledge of ARM AMBA Bus protocols
• Knowledge of C and SystemVerilog.
• Knowledge of UVM verification methodology.
• Experience in C code development for System validation.
• Familiar with scripting language like Perl/Python.