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- Work on SOC strategy and flow definition, integration and implementation.
- Work with System team for P/G pair insertion, pad sequence, bump arrangement and ball arrangement.
- Work on chip test plan, test methodology decision and low power methodology decision.
- Work on synthesis and timing closure, formal verification, ECO flow, netlist analysis/debugging.
- Work on hierarchical flow, design partition and timing budget.
- Work on gate level simulation and vector generation, post silicon bring up and debugging.
- Interpret design specification to create timing constrain script in different modes and corners.
- Run Static Timing Analysis (STA) at the both the block and full chip level using industry standard STA tools.
- Work with designer to clean Lint, CDC, timing violation and achieve pre-layout timing closure.
- Work with APR Engineers to achieve timing closure.
- Develop tcl and dc-shell scripts for performing ECO's.
- Contribute to the ongoing development and enhancement of entire timing methodology.
- Act as a primary implementation technical interface to external vendors, EDA tools, IP suppliers, design services and technology/partners.
- Work with x-function teams to enable differentiated solutions through the application and selection of appropriate technologies at the right time.
- Define and support advanced ASIC implementation methodologies and processes, developing all necessary infrastructures, tools and environment, supporting effective multi-site implementation team collaboration.
- Responsible for the implementation technology roadmap aligned with product development roadmap strategy and industry leaders.