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Principal Verification Engineer

Location: Hsinchu, Hsinchu County, Taiwan 
Req ID: JR-0000027308

Description

Responsibilities:


This position is primarily responsible for block and system level verification. Following is the list of must have attributes:


Must have competencies:

  • Competent in system Verilog, UVM verification flows
  • Coverage driven verification concepts, defining covergroups, assertions etc..
  • dexterity in scripting languages perl / python and understands and familiar with Linux computing environment
  • Modeling using high level transaction level modeling languages
  • Cadence tool set experience with simulation and analysis environment, including coverage collection


Added/ extended skillset:

  • Gate level simulation experience
  • Verification of multiple power domain designs using UPF/CPF
  • Emulation experience and validation of systems in the lab
  • Chip level bring-up in the lab
  • Exposure to verification of complex data/signal processing elements
  • Logic design experience in Verilog/VHDL