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Staff Engineer, HW Design

Location: Hsinchu, Hsinchu County, Taiwan 
Req ID: JR-0000027189

Description

Job Summary:

Do you have a passion working on leading edge technology? Are you passionate about working closely with next generation enterprise SSDs? Are you a fast learner and enjoy synthesizing knowledge in to practice? Western Digital is a leader in the design of world class enterprise class SSD products. We are looking for a strong System Design Engineer to work on next generation enterprise SSD Development Platforms. The candidate must be a highly motivated self-starter who will thrive in this dynamic, cutting-edge environment.  A fundamental part of our strategy is having desirable and powerful Development Platform that enable Engineering teams to deliver products at fast pace. Creating these platforms involves a close partnership between Hardware team, Firmware engineers, ASIC designers, and Program team. We are currently building the next generation and we need you!


Responsibilities:

You are responsible for providing technical leadership in all facets of System development, from microarchitecture through sustenance. You will work with architects and system engineers to define requirements and the microarchitecture for complex FPGA systems running SSD controller functionality. You will implement or provide leadership to an implementation team whose tasks will include writing specifications, understanding ASIC SoC, partitioning the design, creating custom IPs for FPGA systems, making RTL changes to map the design into FPGA system and bringing up these systems using system tools. You will also participate in documentation and defining and implementing process for various stages of the development.


Job requirements: 

Understand controller architecture and propose design partitioning to fit within FPGA system's available resources.

Define FPGA delivery milestones and conduct review meeting with wider teams for FPGA platform deliveries.

define interfaces for FPGA partitioning, customize NoCs, design FPGA friendly system clocking and reset scheme based on controller specification.

Must be hands-on when it comes to RTL Coding, creating or customizing IP designs.

Must be able to distribute work to  team members and set reasonable expectation for QoR and timely delivery.

Defining FPGA IO interface, IO constraints, FPGA timing optimization, logic optimization.

Defining streamlined FPGA build flow with nightly builds.

Conduct and review different parts of the design including system level design.

Ability to communicate effectively with other groups such as Architecture group, ASIC design, FPGA HW design group, Firmware team, program management.

Motivated and self-driven. A Team player is a must.

Must be able to read hardware schematic design.

Proficiency with Microsoft Office applications such as Word, Excel, and PowerPoint, Visio is required. 

Qualifications

Qualification:

Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related technical degree is required. 


Required:

Minimum 8 years’ experience in RTL design and System design.

Must have experience designing high density FPGAs, fundamental knowledge of FPGA internal architecture, FPGA IO Design, understanding device utilization and Vendor IP selection for FPGAs.

Experience with RTL Simulation tools, Synplify Premier, Identify debugger, Xilinx Vivado, Xilinx ILA, ARM ICE debuggers.

Must have hands-on experience in prototype bring-up and debugging, functional verification.

Experience in small embedded systems, and basic processor and DRAM bringup.

Experience creating and testing Application specific Zynq or Arria FPGA system.


Desired:

Experience working with FPGA development platforms is a definite plus.

Practical experience in hardware debug - use of test equipment (Oscilloscope, Logic Analyzer, Chipscope etc.).

Basic software development experience using C and/or Linux (Perl/Shell scripting) is a plus.