1. Senior level verification engineer and as the lead for the team.
2. Local coordinator for the verification activities and reports to the verification lead for the Venice and future projects
3. Individually contributes towards test plan development and test bench development and to key reusable components
4. Technically observe the team for progress towards a planned verification activities and provide help and technical assistance as and when needed
5. Review all test plans and verification test bench designs.
6. Local Functional manager for the team.
7. Must be an expert with UVM, System Verilog and modern verification methodologies
8. Exposure to design and gate level simulations is a plus.
1. Masters in EE/ECE
2. Excellent communication skills and dexterity in in spoken and written English.
3. 10+ years of hands on experience in System on Chip and Module level complex IP verification.
4. 3+ years of lead role experience