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Principal Engineer FPGA RTL design

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Location: Chubei City, Hsinchu County, Taiwan 
Req ID: 9100001498


FPGA Platforms

Job description
1.Xilinx FPGA development experience. Virtex 7 FPGA preferred
2.Vivado tool experience
3.Able to verify and fit FPGA IO pinout using tool and recommend changes
4.Experience with design timing constraints, timing closure and static timing analysis
5.Experience with FPGA floor planning tool
6.Ability to bring up new FPGA design on boards
7.Experience with PCIe bringup and serdes interconnects on FPGA. Including fitting, constraining and debug. Additional serial interfaces like SAS is a plus
8.DDR3 interface design and testing
9.Write RTL code for FPGA. Also being able to use existing ASIC RTL code and modify to fit on FPGA
10.Able to create partition of Code between multiple FPGAs